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motorola semiconductor technical data 33888 simplified application diagram 33888 33888a this document contains certain information on a new product. specifications and information herein are subject to change without notice. ? motorola, inc. 2004 document order number: mc33888 rev 3.0, 10/2004 product preview +5.0 v +5.0 v fsi fs mcu a/d a/d csns0-1 csns2-3 wdin spi ihs0:ihs3 ils rst v dd 4 4 gnd v pwr ls4:ls11 hs3 hs2 hs1 hs0 loads 8 x relay or led 33888 v pwr ordering information device temperature range (t a ) package pc33888pnb/r2 -40c to 125c 36 pqfn pc33888apnb/r2 mc33888fb/r2 64 pqfp quad high-side and octal low-side switch for automotive the 33888 is a single-package combination of a power die with four discrete high-side mosfets (two 10 m ? and two 40 m ?) and an integrated ic control die consisting of eight low-side drivers (600 m ? each) with appropriate control, protecti on, and diagnostic features. programming, control, and diagnostics are accomplished using a 16-bit spi interface. additionally, each high-side output has its own parallel input for pulse-width modulation (pwm) control if desired. the low sides share a single configurable direct input. the 33888 is available i n two power packages. features ? dual 10 m ? high side, dual 40 m ? high side, octal 600 m ? low side ? full operating voltage of 6.0 v to 27 v ? spi control of high-side overcurrent limit, high side current sense, output off open load detection, output on/off control, watchdog timeout ? spi reporting of program status and fault ? high-side analog current feedback with selectable ratio ? enhanced 16 v reverse polarity v pwr protection solid state relay for automotive applications pnb suffix apnb suffix case 1438-06 36-terminal pqfn (12 x 12) bottom view fb suffix case 1315-03 64-terminal pqfp top view f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
33888 motorola analog integrated circuit device data 2 table 1. features comparison: 33888 and 33888a figure 1. 33888 simplified internal block diagram parameter symbol condition 33888 33888a for details, see page undervoltage low-side output shutdown v pwruv ? 5.0 v 3.0 v 11 low-side drain-to-source on resistance r ds(on) v pwr = 4.5 v; v dd = 3.5 v not specified 8.0 ? 14 recommended frequency of spi operation f spi extended mode, v dd = 3.4 v not specified 2.1 mhz (max) 17 watchdog overtemperature detection open load detection logic spi 3.0 mhz selectable current limit internal regulator gate driver over/undervoltage protection hs0 v pwr v dd cs sclk so si rst wake fs in0 fsi in3 csns0-1 hs0 hs1 hs2 hs3 hs1 hs2 in1 in2 selectable output current recopy (analog mux) v ic v ic i dwn i up i dwn r dwn selectable output current recopy (analog mux) gate control clamp over- temperature i lim open load ls4 ls5 ls6 ls7 ls8 ls9 ls10 ls11 x 8 hs3 csns2-3 gnd 10 m ? gate control and fault 10 m ? gate control and fault 40 m ? gate control and fault 40 m ? ils wdin f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola analog integrated circuit device data 33888 3 terminal definitions for pqfn functional descriptions of many of these terminals can be foun d in the system/application information section beginning on page 19 . terminal terminal name formal name definition 1 fs fault status (active low) this output terminal is an open drain indica tion that goes active low when a fault mode is detected by the devic e. specific device fault indi cation is given via the so terminal. 2, 24 v pwr positive power supply these terminal connects to the positive power supply and are the source input of operational power for the device. 3 6 8 10 ls4 ls6 ls8 ls10 low-side output 4 low-side output 6 low-side output 8 low-side output 10 each low-side terminal is one 0.6 ? low-side output mosfet drain, which pulls current through the connected loads. each of the outputs is actively clamped at 53 v. these outputs are current and thermal overload protected. maximum steady state current through each of these outputs is 500 ma. 4, 11, 15, 20, 32 gnd ground these terminals serve as the ground fo r the source of the low-side output transistors as well as the logic portion of the device. 5 7 9 12 ls5 ls7 ls9 ls11 low-side output 5 low-side output 7 low-side output 9 low-side output 11 each low-side terminal is one 0.6 ? low-side output mosfet drain, which pulls current through the connected loads. each of the outputs is actively clamped at 53 v. these outputs are current and thermal overload protected. maximum steady state current through each of these outputs is 800 ma. 13 v dd digital drain voltage (power) this is an external input terminal us ed to supply power to the spi circuit. transparent top view of package 2 3 13 11 12 10 9 8 7 6 5 4 15 gnd 17 18 19 21 20 22 35 34 33 32 31 30 23 24 v pwr 25 26 27 28 29 1 36 wdin fsi rst wake gnd ihs1 ihs0 csns0-1 sclk cs si ils gnd ihs3 ihs2 csns2-3 hs3 hs1 hs0 hs2 fs v pwr ls4 gnd ls5 ls6 ls7 ls8 ls9 ls10 gnd ls11 v dd so 14 internally connected to v pwr 16 (control die) (power die) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
33888 motorola analog integrated circuit device data 4 14 so serial output this is an output terminal connected to t he spi serial data input terminal of the mcu or to the si terminal of the next device in a daisy chain. this output will remain tri-stated unless the device is selected by a low cs terminal. the output signal generated will have cmos logic levels and the output data will transition on the rising edges of sclk. the serial output da ta provides fault information for each output and is returned msb first when the device is addressed. od11 through od0 are output fault bits for outputs 11 through 0, respectively. 16 cs chip select (active low) this is an input terminal connected to a chip select output of a microcontroller (mcu). this ic controls which device is addressed (select ed) by pulling the cs terminal of the desired de vice logic low, enabling the spi communication with the device, while other devices on the serial link keep their serial outputs tri-stated. this input has an internal active pullu p and requires cmos logic levels. 17 sclk serial clock this input terminal is connec ted to the sclk terminal of the master mcu, which is a bit (shift) clock for the spi port. it trans itions one time per bit transferred at an operating frequency, f spi , and is idle between command transfers. it is 50% duty cycle and has cmos logic leve ls. this signal is used to shift data to and from the 33888. 18 si serial input this input terminal is connected to the spi serial data output terminal of the mcu from which it receives output command dat a. this input has an internal active pull-down and requires cmos logic levels. t he serial data transmitted on this line is a 16-bit control command sent msb fi rst, which controls the twelve output channels. bits d3:d0 control the high-side outputs hs3:hs0, respectively. bits d11:d4 control the low-side outputs ls11:ls 4, respectively. the muc will ensure that data is available on the falling edge of sclk. 19 ils low-side input this input terminal is used to directly control a number of the low-side devices as configured by spi. this terminal ma y or may not be activated depending on the configured state of the internal logic. 21 22 30 31 ihs3 ihs2 ihs0 ihs1 high-side input 3 high-side input 2 high-side input 0 high-side input 1 each high-side input terminal is used to directly control only one designated high- side output. these inputs may or may not be activated depending on the configured state of the internal logic. 23 29 csns2-3 csns0-1 current sense 2-3 current sense 0-1 these terminals deliver a ratioed amount of the high-side output current that can be used to generate signal ground referenced output voltages for use by the mcu. each respective csns terminal can be c onfigured via spi to deliver current from either of the two assigned outputs, or the currents could be the sum of the two. current from hs0 and/or hs1 are sensed via csns0-1. current from hs2 and/or hs3 are sensed via csns2-3. 25 28 hs3 hs2 high-side output 3 high-side output 2 each terminal is the source of a 40 m ? mosfet high-side dr iver, which delivers current through the connected loads. t hese outputs can be controlled via spi or using the ihs terminals depending on the inte rnal configuration. these outputs are current limited and thermally protected. during fail-safe mode, output hs2 will be turned on until the device is reinitiali zed and then immediately followed by normal operation. 26 27 hs1 hs0 high-side output 1 high-side output 0 each terminal is the source of a 10 m ? mosfet high-side dr iver, which delivers current through the connected loads. t hese outputs can be controlled via spi or using the ihs terminals depending on the inte rnal configuration. these outputs are current limited and thermally protected. during fail-safe mode, output hs0 will be turned on until the device is reinitiali zed and then immediately followed by normal operation. 33 wake wake this terminal is used to input a logic [1] signal in order to enable the watchdog timer function. an internal clamp protects the terminal from high voltages when current is limited with an external resistor. this input has a passive internal pulldown. terminal definitions for pqfn (continued) functional descriptions of many of these terminals can be fo und in the system/application information section beginning on page 19 . terminal terminal name formal name definition f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola analog integrated circuit device data 33888 5 34 rst reset (active low) this input terminal is used to initialize the device configuration and fault registers, as well as place the device in a low current standby mode. this terminal also starts the watchdog timeout when transitioned from logic [0] to logic [1]. this terminal should not be allowed to be at logic [1] until v dd is in regulation. this input has an internal passive pulldown. 35 fsi fail-safe input the fail-safe input terminal level determines the state of the outputs after a watchdog timeout occurs. this terminal has an internal pullup. if the fsi terminal is left to float to a logic [1], then hs0 and hs2 will turn on when in the fail-safe state. if the fsi terminal is tied to gnd, the wa tchdog circuit and fail-safe operation will be disabled, thus allowing oper ation without a watchdog signal. 36 wdin watchdog input this input terminal is a cm os logic level input that is used to monitor system operation. if the incoming watchdog signal does not transition within the normal watchdog timeout range, the device will operate in the fail-safe mode. this input has an active internal pulldown. terminal definitions for pqfn (continued) functional descriptions of many of these terminals can be fo und in the system/application information section beginning on page 19 . terminal terminal name formal name definition f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
33888 motorola analog integrated circuit device data 6 terminal definitions for pqfp functional descriptions of many of these terminals can be fo und in the system/application information section beginning on page 19 . terminal terminal name formal name definition 1 fsi fail-safe input the fail-safe input terminal level determines the state of the outputs after a watchdog timeout occurs. this terminal has an internal pullup. if the fsi terminal is left to float to a logic [1], then hs0 and hs2 will turn on when in the fail-safe state. if the fsi terminal is tied to gnd, the watchdog circuit and fail-safe operation will be disabled, thus allowing oper ation without a watchdog signal. 2 wdin watchdog input this input terminal is a cmos logic leve l input that is used to monitor system operation. if the incoming watchdog signal does not transition within the normal watchdog timeout range, the device will operate in the fail-safe mode. this input has an active internal pulldown. 3 fs fault status (active low) this output terminal is an open drain indi cation that goes active low when a fault mode is detected by the device. specific devi ce fault indication is given via the so terminal. 4, 26, 27, 58, 59 v pwr positive power supply these terminal connects to the positive power supply and are the source input of operational power for the device. 5 8 11 14 ls4 ls6 ls8 ls10 low-side output 4 low-side output 6 low-side output 8 low-side output 10 each low-side terminal is one 0.6 ? low-side output mosfet drain, which pulls current through the connected loads. each of the outputs is actively clamped at 53 v. these outputs are current and thermal overload protected. maximum steady state current through each of these outputs is 500 ma. 6, 9, 12, 15 gnd ground these terminals serve as the ground for the source of the low-side output transistors as well as the logic portion of the device. fsi 1 gnd ls5 ls6 ls8 ls11 v dd so cs sclk gnd ls9 ls10 gnd gnd ls7 ls4 v pwr fs wdin nc hs0 hs0 hs0 hs1 hs1 hs1 nc nc nc hs1 hs1 hs1 hs1 hs0 hs0 hs0 hs0 nc nc v pwr nc nc nc hs2 hs2 si v pwr csns2-3 ihs2 ihs3 ils v pwr nc nc nc hs3 hs3 14 15 16 17 18 19 20 8 9 10 12 13 11 4 5 6 7 3 2 64 61 60 59 62 63 21 24 25 26 23 22 27 30 31 32 29 28 52 39 38 37 36 35 34 33 45 44 43 41 40 42 49 48 47 46 50 51 58 55 54 53 56 57 rst v pwr csns0-1 ihs0 ihs1 wake f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola analog integrated circuit device data 33888 7 7 10 13 16 ls5 ls7 ls9 ls11 low-side output 5 low-side output 7 low-side output 9 low-side output 11 each low-side terminal is one 0.6 ? low-side output mosfet drain, which pulls current through the connected loads. each of the outputs is actively clamped at 53 v. these outputs are current and thermal overload protected. maximum steady state current through each of these outputs is 800 ma. 17 v dd digital drain voltage (power) this is an external input terminal us ed to supply power to the spi circuit. 18 so serial output this is an output terminal connected to t he spi serial data input terminal of the mcu or to the si terminal of the next device in a daisy chain. this output will remain tri-stated unless the device is selected by a low cs terminal. the output signal generated will have cmos logic levels and the output data will transition on the rising edges of sclk. the serial output da ta provides fault information for each output and is returned msb first when the device is addressed. od11 through od0 are output fault bits for outputs 11 through 0, respectively. 19 cs chip select (active low) this is an input terminal connected to a chip select output of a microcontroller (mcu). this ic controls which device is addressed (select ed) by pulling the cs terminal of the desired de vice logic low, enabling the spi communication with the device, while other devices on the serial link keep their serial outputs tri-stated. this input has an internal active pullu p and requires cmos logic levels. 20 sclk serial clock this input terminal is connec ted to the sclk terminal of the master mcu, which is a bit (shift) clock for the spi port. it trans itions one time per bit transferred at an operating frequency, f spi , and is idle between command transfers. it is 50% duty cycle and has cmos logic levels . this signal is used to shift data to and from the 33888. 21 si serial input this input terminal is connected to the spi serial data output terminal of the mcu from which it receives output command dat a. this input has an internal active pull-down and requires cmos logic levels. t he serial data transmitted on this line is a 16-bit control command sent msb fi rst, which controls the twelve output channels. bits d3:d0 control the high-side outputs hs3:hs0, respectively. bits d11:d4 control the low-side outputs ls11:ls 4, respectively. the muc will ensure that data is available on the falling edge of sclk. 22 ils low-side input this input terminal is used to directly control a number of the low-side devices as configured by spi. this terminal ma y or may not be activated depending on the configured state of the internal logic. 23 24 61 62 ihs3 ihs2 ihs0 ihs1 high-side input 3 high-side input 2 high-side input 0 high-side input 1 each high-side input terminal is used to directly control only one designated high- side output. these inputs may or may not be activated depending on the configured state of the internal logic. 25 60 csns2-3 csns0-1 current sense 2-3 current sense 0-1 these terminals deliver a ratioed amount of the high-side output current that can be used to generate signal ground referenced output voltages for use by the mcu. each respective csns terminal can be conf igured via spi to deliver current from either of the two assigned outputs, or the currents could be the sum of the two. current from hs0 and/or hs1 are sensed via csns0-1. current from hs2 and/or hs3 are sensed via csns2-3. 28, 29 56, 57 hs3 hs2 high-side output 3 high-side output 2 each terminal is the source of a 40 m ? mosfet high-side driver, which delivers current through the connected loads. thes e outputs can be controlled via spi or using the ihs terminals depending on the inte rnal configuration. these outputs are current limited and thermally protected. during fail-safe mode, output hs2 will be turned on until the device is reinitiali zed and then immediately followed by normal operation. 30?35, 50?55 nc not connected these terminals are not connected internally. terminal definitions for pqfp (continued) functional descriptions of many of these terminals can be fo und in the system/application information section beginning on page 19 . terminal terminal name formal name definition f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
33888 motorola analog integrated circuit device data 8 36?42 43?49 hs1 hs0 high-side output 1 high-side output 0 each terminal is the source of a 10 m ? mosfet high-side dr iver, which delivers current through the connected loads. t hese outputs can be controlled via spi or using the ihs terminals depending on the inte rnal configuration. these outputs are current limited and thermally protected. during fail-safe mode, output hs0 will be turned on until the device is reinitiali zed and then immediately followed by normal operation. 63 wake wake this terminal is used to input a logic [1] signal in order to enable the watchdog timer function. an internal clamp protects the terminal from high voltages when current is limited with an external resistor. this input has a passive internal pulldown. 64 rst reset (active low) this input terminal is used to initialize the device configuration and fault registers, as well as place the device in a low current standby mode. this terminal also starts the watchdog timeout when transitioned from logic [0] to logic [1]. this terminal should not be allowed to be at logic [1] until v dd is in regulation. this input has an internal passive pulldown. terminal definitions for pqfp (continued) functional descriptions of many of these terminals can be fo und in the system/application information section beginning on page 19 . terminal terminal name formal name definition f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola analog integrated circuit device data 33888 9 maximum ratings all voltages are with respect to ground unless otherwise noted. rating symbol value unit electrical ratings power supply voltage steady state v pwr -16 to 41 v input terminal voltage (note 1) v in -0.3 to 7.0 v wake input terminal clamp current i wici 2.5 ma continuous per output current (note 2) low-sides 4, 6, 8, 10 low-sides 5, 7, 9, 11 i outls 500 800 ma continuous per output current (note 3) high-sides 0, 1 high-sides 2, 3 i ouths 10 5.0 a output clamp energy high-sides 0, 1 (note 4) high-sides 2, 3 (note 5) low-sides (note 6) e hs e hs e ls 450 120 50 mj esd voltage human body model (note 7) machine model (note 8) v esd1 v esd2 2000 200 v notes 1. exceeding voltage limits on sclk, si, cs , wdin, rst , ihs, fsi, or ils terminals may cause a malfunction or permanent damage to the device. 2. continuous low-side output current rating so long as maximum junction temperature is not exceeded. operation at 125c ambient temperature will require calculation of maximu m output current using package thermal resistance. 3. continuous high-side output current rating so long as maximu m junction temperature is not exceeded. operation at 125c ambien t temperature will require calculation of maximu m output current using package thermal resistance. 4. active hs0 and hs1 clamp energy using the fo llowing conditions: singl e nonrepetitive pulse, v pwr = 16.0 v, l = 40 mh, t j = 150c. 5. active hs2 and hs3 clamp energy using the fo llowing conditions: singl e nonrepetitive pulse, v pwr = 16.0 v, l = 10 mh, t j = 150c. 6. active low-side clamp energy using the follow ing conditions: single nonrepetitive pulse, 450 ma, t j = 150c. 7. esd1 testing is performed in accordance with the human body model (c zap =100 pf, r zap = 1500 ? ). 8. esd2 testing is performed in ac cordance with the machine model (c zap = 200 pf, r zap = 0 ? ). f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
33888 motorola analog integrated circuit device data 10 thermal ratings operating temperature ambient junction t a t j -40 to 125 -40 to 150 c storage temperature t stg -55 to 150 c control die thermal resistance (note 9) pqfp one low-side on two low-side on three low-side on four low side on all low-sides on pqfn one low-side on two low-side on three low-side on four low side on all low-sides on r cjc 12.5 9.3 7.3 5.9 3.2 8.6 6.0 4.6 3.8 2.0 c/w power die thermal resistance (note 9) pqfp one high-side 2, 3 on all high-sides on pqfn one high-side 2, 3 on all high-sides on r pjc 0.5 0.15 0.5 0.1 c/w thermal resistance, junction to ambi ent, natural convection, four-layer board (note 9) pqfp pqfn r ja 33 37 c/w peak terminal reflow temperature during solder mounting (note 10) pqfp pqfn t solder 225 240 c notes 9. board dimensions are 8.0 cm x 8.0 cm x 1.5 mm with a 300 mm 2 copper area on the bottom layer. 10. terminal soldering temperature limit is 10 seconds maximum duration. not designed fo r immersion soldering. exceeding these l imits may cause malfunction or permanent damage to the device. maximum ratings (continued) all voltages are with respect to ground unless otherwise noted. rating symbol value unit f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola analog integrated circuit device data 33888 11 static electrical characteristics characteristics noted under conditions 6.0 v v pwr 27 v, 4.5 v v dd 5.5 v, -40 c t j 150 c unless otherwise noted. typical values noted reflect the approximate parameter mean at t a = 25 c under nominal conditions unless otherwise noted. characteristic symbol min typ max unit power input supply voltage range fully operational v pwr 6.0 ? 27 v v pwr supply current t j > 125c t j 125c i pwr(on) ? ? 17 ? 25 20 ma v pwr standby current (all outputs off, open load detection disabled, wake = h, rst = h) t j > 125c t j 125c i pwr(sby) ? ? 4.2 2.9 7.0 5.0 ma sleep state supply current (v pwr < 12.6 v, rst < 0.5 v, wake < 0.5 v, hs[0:3] = 0 v) (note 11) t j = 85c t j = 25c i pwr(ss) ? ? ? 1.0 80 25 a logic supply voltage range v dd 4.5 5.0 5.5 v logic supply current t j > 125c t j 125c i dd(on) ? ? 4.2 2.9 7.0 5.0 ma logic supply sleep state current i dd(ss) ??5.0 a sleep state low-side output leakage current (per low-side output, rst = low) t j = 85c t j = 25c i slk(ss) ? ? ? ? 3.0 1.0 a overvoltage shutdown threshold v pwrov 28 . 532 36v overvoltage shutdown hysteresis v pwrov(hys) 0.2 0.6 1.5 v undervoltage high-side output shutdown (note 12) v pwruv 5.0 5.6 6.0 v undervoltage low-side output shutdown apnb suffix only (note 12) pnb and fb suffixes v pwruv 3.0 5.0 4.0 5.6 4.4 6.0 v undervoltage high-side shutdown hysteresis v pwruv(hys) 0.1 0.3 0.5 v notes 11. this parameter is tested at 125c with a maximum value of 10 a. 12. spi/io and internal logic operational. outputs will recover in instructed state when v pwr voltage level returns to normal as long as the level does not go below v pwruv . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
33888 motorola analog integrated circuit device data 12 power input (continued) current sense ratio (9.0 v < v pwr < 16 v, csns < 4.5 v) csns0-1/hs0, csns0-1/hs1 c sr[0:1] ? 1/1400 ? ? current sense ratio (c sr[0:1] ) accuracy hs[0:1] output current 1.0 a 2.0 a 5.0 a 6.5 a 10 a c sr[0:1]_acc -35 -19 -14 -12 -12 ? ? ? ? ? 35 19 14 12 12 % current sense ratio (v pwr = 9.0 v ? 16 v, csns < 4.5 v) csns2-3/hs2, csns2-3/hs3 c sr ? 1/880 ? ? current sense ratio (c sr[2:3] ) accuracy hs[2:3] output current 0.5 a 1.0 a 3.0 a 3.7 a 5.0 a c sr[2:3]_acc -30 -19 -13.5 -12 -9.0 ? ? ? ? ? 30 19 13.5 12 9.0 % current sense clamp voltage i cns = 15 ma generated by the device v sense 4.5 6.0 7.0 v hs0 and hs1 power outputs drain-to-source on resistance (i out = 5.5 a) t j = 25c v pwr = 6.0 v v pwr = 9.0 v v pwr = 13 v t j = 150c v pwr = 6.0 v v pwr = 9.0 v v pwr = 13 v r ds(on) ? ? ? ? ? ? ? ? ? ? ? ? 0.02 0.01 0.01 0.034 0.017 0.017 ? reverse battery source-to-drain on resistance (i out = -5.5 a, t j = 25c) v pwr = -12 v r ds(on)rev ? ? 0.02 ? output self-limiting peak current outputs on, v out = v pwr -2.0 v i lim(pk) 33 49 66 a output self-limiting sustain current outputs on, v out = v pwr -2.0 v i lim(sus) 13 25 34 a open load detection current (note 13) i oldc 30 ? 100 a notes 13. output off open load detection current is the current required to flow through the load for the purpose of detecting the exi stence of an open load condition when the specific output is commanded off. static electrical charac teristics (continued) characteristics noted under conditions 6.0 v v pwr 27 v, 4.5 v v dd 5.5 v, -40 c t j 150 c unless otherwise noted. typical values noted reflect the approximate parameter mean at t a = 25 c under nominal conditions unless otherwise noted. characteristic symbol min typ max unit f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola analog integrated circuit device data 33888 13 hs0 and hs1 power outputs (continued) output fault detection threshold (note 14) output programmed off v ofd(thres) 2.0 3.0 4.0 v output negative clamp voltage 0.5 a < i out < 2.0 a, output off v cl -20 ? ? v overtemperature shutdown (outputs off) (note 15) t sd 160 175 190 c overtemperature shutdown hysteresis (note 15) t sd(hys) 10 ? 30 c hs2 and hs3 power outputs drain-to-source on resistance (i out = 4.5 a) t j = 25c v pwr = 6.0 v v pwr = 9.0 v v pwr = 13 v t j = 150c v pwr = 6.0 v v pwr = 9.0 v v pwr = 13 v r ds(on) ? ? ? ? ? ? ? ? ? ? ? ? 0.08 0.04 0.04 0.136 0.068 0.068 ? reverse battery source-to-drain on resistance (i out = 4.5 a, t j = 25c) v pwr = -12 v r ds(on)rev ? ? 0.08 ? output self-limiting peak current outputs on, v out = v pwr -2.0 v i lim(pk) 15 23 35 a output self-limiting sustain current outputs on, v out = v pwr -2.0 v i lim(sus) 6.0 10 15 a open load detection current (note 16) i oldc 25 ? 100 a output fault detection threshold (note 17) outputs programmed off v ofd(thres) 2.0 3.0 4.0 v output negative clamp voltage 0.5 a < i out < 2.0 a, outputs off v cl -20 ? ? v overtemperature shutdown (outputs off) (note 18) t sd 160 170 190 c overtemperature shutdown hysteresis (note 18) t sd(hys) 10 ? 30 c notes 14. output fault detection threshold with outputs programmed off. for the low-side outputs, fault detection thresholds are the s ame for output open and battery shorts. 15. guaranteed by design. not production tested. 16. output off open load detection current is the current required to flow through the load for the purpose of detecting the exi stence of an open load condition when the specific output is commanded off. 17. output fault detection threshold with outputs programmed off. 18. guaranteed by design. not production tested. static electrical charac teristics (continued) characteristics noted under conditions 6.0 v v pwr 27 v, 4.5 v v dd 5.5 v, -40 c t j 150 c unless otherwise noted. typical values noted reflect the approximate parameter mean at t a = 25 c under nominal conditions unless otherwise noted. characteristic symbol min typ max unit f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
33888 motorola analog integrated circuit device data 14 low-side power outputs drain-to-source on resistance (i out = 0.3 a) t j = 25c v pwr = 4.5 v; v dd = 3.5 v, 33888a only v pwr = 6.0 v v pwr = 9.0 v v pwr = 13 v t j = 150c v pwr = 4.5 v; v dd = 3.5 v, 33888a only v pwr = 6.0 v v pwr = 9.0 v v pwr = 13 v r ds(on) ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? 8.0 1.0 0.7 0.6 8.0 1.8 1.1 0.9 ? output self-limiting current (outputs programmed on, v out = 3.0 v) low-side 4, 6, 8, 10 low-side 5, 7, 9, 11 i lim 0.5 0.8 0.9 1.3 1.5 2.0 a output off open load detection current (note 19) output programmed off, v out = 3.0 v i oldc 25 50 100 a output fault detection threshold (note 20) output programmed off v ofd(thres) 2.0 3.0 4.0 v output clamp voltage 2.0 ma < i out < 200 ma, outputs off v cl 41 53 60 v low-side body diode voltage (i = -300 ma, t j = 125c) v bd 0.5 0.7 0.9 v overtemperature shutdown (outputs off) (note 21) t lim 160 170 190 c overtemperature shutdown hysteresis (note 21) t lim(hys) 10 20 30 c notes 19. output off open load detection current is the current required to flow through the load for the purpose of detecting the exi stence of an open load condition when the specific output is commanded off. 20. output fault detection threshold with outputs programmed off. for the low-side outputs, fault detection thresholds are the s ame for output open and battery shorts. 21. guaranteed by design. not production tested. static electrical charac teristics (continued) characteristics noted under conditions 6.0 v v pwr 27 v, 4.5 v v dd 5.5 v, -40 c t j 150 c unless otherwise noted. typical values noted reflect the approximate parameter mean at t a = 25 c under nominal conditions unless otherwise noted. characteristic symbol min typ max unit f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola analog integrated circuit device data 33888 15 control interface input logic high voltage (note 22) v ih 0.7 v dd ??v input logic low voltage (note 22) v il ??1.0v input logic voltage hysteresis (si, cs , sclk, ihs[0:3], ils) (note 23) v in(hys) 100 350 750 mv input logic pulldown current (si, sclk, ihs[0:3], ils, wdin) i dwn 5.0 ? 20 a input logic pulldown resistor (wake, rst ) r dwn 100 200 400 k ? input logic pullup current ( cs , v in = 0.7 v dd ) (note 24) i upc 5.0 ? 20 a input logic pullup current (fsi, v in = 3.5 v) i upf 5.0 ? 20 a wake input clamp voltage (i wici < 2.5 ma) (note 25) v wic 7.0 ? 14 v wake input forward voltage (i wici = -2.5 ma) v wif -2.0?-0.3v so high-state output voltage (i oh = 1.0 ma) v soh 0.8 v dd ??v fs , so low-state output voltage (i ol = -1.6 ma) v sol ?0.20.4v so tri-state leakage current ( cs 3.5 v) i solk -5.0 0 5.0 a input capacitance (note 26) c in ? 4.0 12 pf so, fs tri-state capacitance (note 23) c so ? ? 20 pf notes 22. upper and lower logic thres hold voltage range applies to si, cs , sclk, rst , ihs[0:3], ils, wake, and wdin input signals. the wake, fsi, and rst signals are derived from an internal supply. 23. parameter is guaranteed by design but is not production tested. 24. cs is pulled up to v dd . 25. the current must be limited by a series re sistor when using voltages higher than the w icv . 26. input capacitance of si, cs , sclk, rst , ihs[0:3], ils, wake, and wdin. this parameter is guaranteed by process monitoring but is not production tested. static electrical charac teristics (continued) characteristics noted under conditions 6.0 v v pwr 27 v, 4.5 v v dd 5.5 v, -40 c t j 150 c unless otherwise noted. typical values noted reflect the approximate parameter mean at t a = 25 c under nominal conditions unless otherwise noted. characteristic symbol min typ max unit f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
33888 motorola analog integrated circuit device data 16 dynamic electrical characteristics characteristics noted under conditions 6.0 v v pwr 27 v, 4.5 v v dd 5.5 v, -40 c t j 150 c unless otherwise noted. typical values noted reflect the approximate parameter mean at t a = 25 c under nominal conditions unless otherwise noted. characteristic symbol min typ max unit power output timing high-side output rising fast slew rate (note 27) 6.0 v < v pwr < 9.0 v 9.0 v < v pwr < 16 v 16 v < v pwr < 27 v sr r_fast 0.03 0.05 0.1 ? 0.5 ? 0.6 0.8 1.1 v/ s high-side output rising slow slew rate (note 28) 6.0 v < v pwr < 9.0 v 9.0 v < v pwr < 16 v 16 v < v pwr < 27 v sr r_slow 0.01 0.01 0.01 ? 0.08 ? 0.14 0.18 0.2 v/ s high-side output falling fast slew rate (note 27) 6.0 v < v pwr < 9.0 v 9.0 v < v pwr < 16 v 16 v < v pwr < 27 v sr f_fast 0.2 0.3 0.5 ? 0.8 ? 1.0 1.5 2.2 v/ s high-side output falling slow slew rate (note 28) 6.0 v < v pwr < 9.0 v 9.0 v < v pwr < 16 v 16 v < v pwr < 27 v sr f_slow 0.05 0.08 0.08 ? 0.15 ? 0.3 0.4 0.5 v/ s high-side output turn on delay time (note 29) t dly(on) 5.0 30 150 s high-side output turn off delay time (note 30) t dly(off) 5.0 80 150 s low-side output falling slew rate (note 31) sr f 0.5 3.0 10 v/ s low-side output rising slew rate (note 31) sr r 1.0 6.0 20 v/ s low-side output turn on delay time (note 32) t dly(on) 0.5 2.0 10 s low-side output turn off delay time (note 33) t dly(off) 0.5 4.0 10 s low-side output fault delay timer (note 34) t dly( fs ) 70 150 250 s watchdog timeout (note 35) t wdto 340 584 770 ms notes 27. high-side output rise and fall fast slew rates measured across a 5.0 ? resistive load at high-side output = 0.5 v to v pwr -3.0 v (see figure 2 , page 18). these parameters are guaranteed by process monitoring. 28. high-side output rise and fall slow slew rates measured across a 5.0 ? resistive load at high-side output = 0.5 v to v pwr -3.0 v (see figure 2 , page 18). these parameters are guaranteed by process monitoring. 29. high-side output turn-on delay time measured from 50% of the rising ihs to 0.5 v of output off with r l = 27 ? resistive load (see figure 2 , page 18). 30. high-side output turn-off delay time meas ured from 50% of the falling ihs to v pwr -2.0 v of the output off with r l = 27 ? resistive load (see figure 2 , page 18). 31. low-side output rise and fall slew rates measured across a 5.0 ? resistive load at low-side output = 10% to 90% (see figure 3 , page 18). 32. low-side output turn-on delay time measured from 50% of the rising ils to 90% of v out with r l = 27 ? resistive load (see figure 3 , page 18). 33. low-side output turn-off delay time measured from 50% of the falling ils to 10% of v out with r l = 27 ? resistive load (see figure 3 , page 18). these parameters are guaranteed by process monitoring. 34. propagation time of short fault disable r eport delay measured from rising edge of cs to output disabled, low-side = 5.0 v, and device configured for low-side output over current latchoff using cloccr. 35. watchdog timeout delay is measured from the rising edge of wake or rst from the sleep state to the hs[0:1] turn-on with the outputs driven off and the fsi floating. the accuracy of t wdto is maintained for all configured watchdog timeouts. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola analog integrated circuit device data 33888 17 power output timi ng (continued) peak current limit timer (note 36) t pct 40 70 100 ms direct input switching frequency (note 37) f pwm ? 125 ? hz spi interface timing (note 38) recommended frequency of spi operation normal mode extended mode: v dd = 3.4 v; v pwr = 4.5 v, apnb suffix only f spi ? ? ? ? 3.0 2.1 mhz required low state duration for rst (note 39) t wrst ? 50 167 ns rising edge of cs to falling edge of cs (required setup time) (note 40) t cs ? ? 300 ns rising edge of rst to falling edge of cs (required setup time) (note 40) t enbl ??5.0 s falling edge of cs to rising edge of sclk (required setup time) (note 40) t lead ? 50 167 ns required high state duration of sclk (required setup time) (note 40) t wsclkh ? ? 167 ns required low state duration of sclk (required setup time) (note 40) t wsclkl ? ? 167 ns falling edge of sclk to rising edge of cs (required setup time) (note 40) t lag ? 50 167 ns si to falling edge of sclk (required setup time) (note 40) t si(su) ?2583ns falling edge of sclk to si (required hold time) (note 40) t si(hold) ?2583ns so rise time c l = 200 pf t rso ?2550 ns so fall time c l = 200 pf t fso ?2550 ns si, cs , sclk, incoming signal rise time (note 41) t rsi ? ? 50 ns si, cs , sclk, incoming signal fall time (note 41) t fsi ? ? 50 ns time from falling edge of cs to so low impedance (note 42) t so(en) ? ? 145 ns time from rising edge of cs to so high impedance (note 43) t so(dis) ? 65 145 ns time from rising edge of sclk to so data valid (note 44) 0.2 v dd so 0.8 v dd , c l = 200 pf t valid ? 65 105 ns notes 36. t pct measured from the rising edge of cs to 90% of i limpkhs[x,x] when the peak current limit is enabled. 37. this frequency is a typical value. maximum switching frequencie s are dictated by the turn-on delay, turn-off delay, output r ise and fall times, and the maximum allowable junction temperature. 38. symmetrical 50% duty cycle sclk clock period of 333 ns. 39. rst low duration measured with outputs enabled and going to off or disabled condition. 40. maximum setup time required for the 33888 is the minimum guaranteed time needed from the mcu. 41. rise and fall time of incoming si, cs , and sclk signals suggested for des ign consideration to prevent the occurrence of double pulsing. 42. time required for output status data to be available for use at so. 1.0 k ? pullup on cs. 43. time required for output status data to be terminated at so. 1.0 k ? pullup on cs. 44. time required to obtain valid data out from so following the rise of sclk. dynamic electrical characteristics (continued) characteristics noted under conditions 6.0 v v pwr 27 v, 4.5 v v dd 5.5 v, -40 c t j 150 c unless otherwise noted. typical values noted reflect the approximate parameter mean at t a = 25 c under nominal conditions unless otherwise noted. characteristic symbol min typ max unit f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
33888 motorola analog integrated circuit device data 18 timing diagrams figure 2. output slew rates and time delays, high side figure 3. output slew rat es and time delays, low side vpwr vpwr - 0.5v vpwr - 3v 0.5v tdly ( off) srr_fast srr_slow srf_fast srf_slow direct input or spi bit tdly (on) v pwr v pwr -0.5 v v pwr -3.0 v t dly(off) direct input or spi bit sr f_slow sr f_fast sr r_slow sr r_fast t dly(on) 0.5 v tdly(on) vpwr 90% 10% tdly(off) srf srr direct input or spi bit t dly(on) t dly(off) sr r sr f v pwr 90% 10% direct input or spi bit f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola analog integrated circuit device data 33888 19 system/application information introduction this 33888 is a single-package combination of a power die with four discrete high-side mo sfets and an integrated ic control die consisting of eight low-side drivers with appropriate control, protection, and diagn ostic features. the high-side drivers are useful for both internal and external vehicle lighting applications as well as capable of driving inductive solenoid loads. the low-side drivers are capable of controlling low- current on/off type inductive loads, such as relays and solenoids as well as led indicators and small lamps (see simplified application diagram, page 2 ). the device is useful in body control, instrumentation, and other high-power switching applications and systems. the 33888 is available in two packages: a power-enhanced 12 x 12 nonleaded power qfn package with exposed tabs and a 64-lead power qfp plastic package. both packages are intended to be soldered directly onto the printed circuit board. the 33888 differs from the 33888a as explained in table 1 , page 2. functional description spi interface and protocol description the spi interface has full duplex, three-wire synchronous data transfer and has four i/o lines associated with it: serial clock (sclk), serial input (si), serial output (so), and chip select ( cs ). the si/so terminals of the 33888 follow a first-in first-out (d15/d0) protocol with both in put and output words transferring the most significant bit first. all inputs are compatible with 5.0 v cmos logic levels. during spi out put control, a logic [0] in a message word will result in t he designated output being turned off. similarly, a logic [1] will turn on a corresponding output. the spi lines perform the following functions: serial clock (sclk) the sclk terminal clocks the inte rnal shift registers of the 33888. the serial input (si) terminal accepts data into the input shift register on the falling edge of the sclk signal while the serial output terminal (so) shifts data information out of the so line driver on the rising edge of the sclk signal. it is important that the sclk terminal be in a logic [0] state whenever the chip select ( cs ) makes any transition. for this reason, it is recommended that the sclk termina l be kept in a logic [0] state as long as the device is not accessed ( cs in logic [1] state). sclk has an active internal pulldown, i dwn . when cs is logic [1], signals at the sclk and si terminals are ignored and so is tri-stated (high impedance). (see figures 4 and 5 on page 20 .) serial interface (si) this is a serial interface (si) command data input terminal. each si bit is read on the falling edge of sclk. a 16-bit stream of serial data is required on the si terminal, starting with d15 to d0. the 12 outputs of the 33888 are configured and controlled using the 3-bit addressing scheme and the 12 assigned data bits designed into the 33888. si has an active internal pulldown, i dwn . serial output (so) the so data terminal is a tri-stateable output from the shift register. the so terminal remains in a high-impedance state until the cs terminal is put into a logic [0] state. the so data report the status of the output s as well as provide the capability to reflect the state of the direct inputs. the so terminal changes states on the rising edge of sclk and reads out on the falling edge of sclk. when an output is on or off and not faulted, the corresponding so bit, od11:od0, is a logic [0]. if the output is faulted, the corresponding so state is a logic [1]. so od14:od12 reflect the state of six various inputs (three at a time) depending upon the reported state of the previously written watchdog bit od15. chip select ( cs ) the cs terminal enables communication with the master microcontroller (mcu). when this te rminal is in a logic [0] state, the 33888 is capable of transferring information to and receiving information from the mcu. the 33888 latches in data from the input shift registers to the addressed registers on the rising edge of cs . the 33888 transfers status information from the power outputs to the shift registers on the falling edge of cs . the output driver on the so terminal is enabled when cs is logic [0]. cs is only transitioned from a logic [1] state to a logic [0] state when sclk is a logic [0]. cs has an active internal pullup, i up . the 33888 is capable of commun icating directly with the mcu via the 16-bit spi protocol as described in the next section. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
33888 motorola analog integrated circuit device data 20 figure 4. single 16-bit word spi communication figure 5. multiple 16-bit word spi communication serial input communication spi communication is accomplished using 16-bit messages. a message is transmitted by t he mcu starting with the msb, d15, and ending with the lsb, d0 (refer to table 2 , page 21). each incoming command message on the si terminal can be interpreted using the following bit assignments: the first twelve lsbs, d11:d0, control each of the twelve outputs; the next three bits, d14:d12, determine the command mode; and the msb, d15, is the watchdog bit. multiple messages can be transmitted in succession to accommodate those applications where daisy chaining is desirable or to confirm transmitted data, as long as the messages are all multiples of 16 bits. any attempt made to latch in a message that is not 16 bits will be ignored. the 33888 has six registers that are used to configure the device and control the state of the four high-side and eight low-side outputs ( table 3 , page 21). the registers are addressed via d14:d12 of the incoming spi word ( table 2 , page 21). csb si sclk d15 d1 d2 d3 d4 d5 d6 d7 d8 d9 d14 d13 d12 d11 d10 od12 d0 od13 od14 od15 od6 od7 od8 od9 od10 od11 od1 od2 od3 od4 od5 od0 so 1. rst is in a logic [1] state during the above operation. 2. d15:d0 relate to the most recent ordered entry of program data into the 33888. 3. od15:od0 relate to the first 16 bits of ordered fault and status data out of the 33888. notes cs csb si sclk d15 d1* d2* d13* d14* d15* d0 d1 d14 d13 d2 d0* od13 od14 od15 d14 d15 od0 od1 od2 d1 d2 d13 d0 so 1. rst is a logic [1] state during the above operation. 2. d15:d0 relate to the most recent ordered entry of program data into the 33888. 3. d15*:d0* relate to the first 16 bits of ordered entry data out of the 33888. notes 4. od15:od0 relate to the first 16 bits of ordered fault and status data out of the 33888. cs f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola analog integrated circuit device data 33888 21 . device register addressing the following section describes the possible register addresses and their impact on device operation. address 000?spi output control register (socr) the socr register allows the m cu to control the outputs via the spi. incoming message bits d3:d0 reflect the desired states of high-side outputs hs3:hs0. message bits d11:d4 reflect the desired state of low-side outputs ls11:ls4, respectively. address 100?direct input control register (dicr) the dicr register is used by the mcu to enable direct input control of the outputs. for the outp uts, a logic [0] on bits d11:d0 will enable the corresponding ou tput for direct control. a logic [1] on a d11:d0 bit will di sable the output from direct control. address 010?logic function control register (lfcr) the lfcr register is used by the mcu to configure the relationship between socr bits d 11:d0 and the direct inputs ihs[0:3] and ils. while addressing this register (if the direct inputs were enabled for direct c ontrol with the dicr), a logic [1] on any or all of the d3:d0 bits will result in a boolean and of the ihs[0:3] terminal(s) with its (their) corresponding d3:d0 message bit(s) when addressing the socr. a logic [1] on any or all of the d11:d4 bits will result in a boolean and of the ils and the corresponding d11:d4 message bits when addressing the socr. similarly, a logic [0] on the d3:d0 bits will result in a boolean or of the ihs[0:3] terminal(s) with their corresponding message bits when addressing the socr register, and the ils will be boolean ored with message bits d11:d4 when addressing the socr register (if ils is enabled). table 2. si message bit assignment bit sig si msg bit message bit description msb d15 watchdog in: toggled to satisfy watchdog requirements. d14:12 register address bits. d11 used to configure low-side output ls11. d10 used to configure low-side output ls10. d9 used to configure low-side output ls9. d8 used to configure low-side output ls8. d7 used to configure low-side output ls7. d6 used to configure low-side output ls6. bit sig si msg bit message bit description d5 used to configure low-side output ls5 (watchdog timeout msb during wdcscr configuration). d4 used to configure low-side output ls4 (watchdog timeout lsb during wdcscr configuration). d3 used to configure high-side output hs3. d2 used to configure high-side output hs2. d1 used to configure high-side output hs1. lsb d0 used to configure high-side output hs0. table 2. si message bit assignment (continued) table 3. serial input address and configuration bit map si register wd address low-side high-side d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 socr x 0 0 0 ls11 ls10 ls9 ls8 ls7 ls6 ls5 ls4 hs3 hs2 hs1 hs0 dicr x 1 0 0 pwb11 pwb10 pwb9 pwb8 pwb7 pwb6 pwb5 pwb4 pwb3 pwb2 pwb1 pwb0 lfcr x 0 1 0 a/ob11 a/ob10 a/ob9 a/ob8 a/ob7 a/ob6 a/ob5 a/ob4 a/ob3 a/ob2 a/ob1 a/ob0 wdcscr x 1 1 0 na na na na na na wdh wdl cs3 cs2 cs1 cs0 olcr x 0 0 1 ol11 ol10 ol9 ol8 ol7 ol6 ol5 ol4 olb3 olb2 olb1 olb0 cloccr x 1 0 1 oc11 oc10 oc9 oc8 oc7 oc6 oc5 oc4 ilim3 ilim2 ilim1 ilim0 not used x 0 1 1 ? ? ? ? ? ? ? ? ? ? ? ? test x 1 1 1 ? ? ? ? ? ? ? ? ilimpk wd ilim ot x=don?t care. na=not applicable. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
33888 motorola analog integrated circuit device data 22 address 110?watchdog and current sense configuration register (wdcscr) the wdcscr register is used by the mcu to configure the watchdog timeout and the csns 0-1 and csns2-3 terminals. the watchdog timeout is configured using bits d4 and d5. the state of d4 and d5 determine the divided value of the wdto. for example, if d5 and d4 are logic [0] and logic [0], respectively, then the wdto wi ll be in the default state as specified in table 3 , page 21. a d5 and a d4 of logic [0] and logic [1] will result in a watchdog timeout of wdto 2. similarly, a d5 and a d4 of logic [1] and logic [0] result in a watchdog timeout of wdto 4, and a d5 and a d4 of logic [1] and logic [1] result in a watchdog timeout of wdto 8. note that when d5 and d4 bits are programmed for the desired watchdog timeout period, the wd bit (d15) should be toggled as well to ensure that the new timeout period is programmed at the beginning of a new count sequence. csns0-1 is the current sens e output for the hs0 and hs1 outputs. similarly, the csns2-3 terminal is the current sense output for the hs2 and hs3 outputs. in this mode, a logic [1] on any or all of the message bits that control the high-side outputs will result in the sensed current from the corresponding output being directed out of the appropriate csns output. for example, if d1 and d0 are both logic [1], then the sensed current from hs0 and hs1 will be summed into the csns0-1. if d2 is logic [1] and d3 is logi c [0], then only the sensed current from hs2 will be directed out of csns2-3. address 001?open load configuration register (olcr) the olcr register allows the mcu to configure each of the outputs for open load fault detection. while in this mode, a logic [1] on any of the d3:d0 message bits will disable the corresponding outputs? circuitry that allows the device to detect open load faults while the output is off. for the low-side drivers, a logic [1] on any of the d11:d4 bits will enable the open load detection circuitry. th is feature allows the mcu to minimize load current in some applications and may be useful to diagnose output shorts to battery (for hs). address 101?current limit overcurrent configuration register (cloccr) the cloccr register allows the mcu to individually override the peak current limit levels for each of the high-side outputs. a logic [1] on any or all of the d3:d0 bit(s) results in the corresponding hs3:hs0 output term inals to current limit at the sustain current limit level. this register also allows the mcu to enable or disable the overcurrent shutdown of the low-side output terminals. a logic [1] on any or all of the d11:d4 message bit(s) will result in the corresponding ls11:ls4 terminals latching off if the current exceeds i lim after a timeout of t dly( fs ) . address 011?not used not currently used. address 111?test the test register is reserved for test and is not accessible via spi during normal operation. serial output communication (devise status return data) when the cs terminal is pulled low, t he output status register for each output is loaded into t he output register and the fault data is clocked out msb (od15) first as the new message data is clocked into the si terminal. od15 reflects the state of the watchdog bit (d15) that was addressed during the prior socr communication (refer to table 4 , page 23). if bit od15 is logic [0], then the three msbs od14:od12 will reflect the logic states of the ihs0, ihs1, and fsi terminals, respectively. if bi t od15 is logic [1], then the same three msb bits will reflect the logic states of the ihs2, ihs3, and wake terminals . the next twelve bits clocked out of so following a low transition of the cs terminal (od11:od0) will reflect the state of each outpu t, with a logic [1] in any of the bits indicating that the respec tive output experienced a fault condition prior to the cs transition. any bits clocked out of the so terminal after the first 16 will be representative of the initial message bits that were clocked into the si terminal since the cs terminal first transitioned to a logic [0]. this feature is useful for daisy chaining devices as well as message verification. following a cs transition logic [0] to logic [1], the device determines if the message was of a valid length (a valid message length is one that is a multiple of 16 bits) and if so, latches the data into the appropriate registers. at this time, the so terminal is tri-stated and the fault status register is now able to accept new fault status information. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola analog integrated circuit device data 33888 23 modes of operation watchdog and fail-safe operation the watchdog is enabled and a timeout is started when the wake or rst transitions from logic [ 0] to logic [1]. the wake input is capable of being pulled up to v pwr with a series limiting resistance that limits the internal clamp current. the timeout is a multiple of an internal oscillator. as long as the wdin terminal or the wd bit (d15) of an incoming spi message is toggled within the minimum watchdog timeout, wdto (or a divided value configured during a wdcscr message), then the device will operate normally. if the watc hdog timeout occurs before the wd bit or the wdin terminal is toggled, then the device will revert to a fail-safe mode until t he device is reinitialized (if the fsi terminal is left disconnected). during fail-safe mode, all outputs will be off except for hs0 and hs2, which will be driven on regardless of the state of the various direct inputs and modes ( table 5 ). the device can be brought out of the fail-sa fe mode by transitioning the wake and rst terminals from logic [1] to logic [0]. in the event the wake terminal was not transi tioned to a lo gic [1] during normal operation and the watchdog times out, then the device can be brought out of fail-safe by bringing the rst to a logic [0]. if the fsi terminal is tied to gnd, then the watchdog, and therefore fail-safe operation, will be disabled. table 4. serial output bit assignment bit sig so msg bit message bit description msb od15 reflects the state of the watchdog bit from the previously cloc ked-in message. od14 if od15 is logic [0], then this bit will reflect the state of the direct input ihs0. if od15 is logic [1], then this bit will reflect the state of ihs2. od13 if od15 is logic [0], then this bit will reflect the state of the direct input ihs1. if od15 is logic [1], then this bit will reflect the state of ihs3. od12 if od15 is logic [0], then this bit will reflect the state of the input fsi. if od15 is l ogic [1], then this bit will reflect the state of the input wake. od11 reports the absence or presence of a fault on ls11. od10 reports the absence or presence of a fault on ls10. bit sig so msg bit message bit description od9 reports the absence or presence of a fault on ls9. od8 reports the absence or presence of a fault on ls8. od7 reports the absence or presence of a fault on ls7. od6 reports the absence or presence of a fault on ls6. od5 reports the absence or presence of a fault on ls5. od4 reports the absence or presence of a fault on ls4. od3 reports the absence or presence of a fault on hs3. od2 reports the absence or presence of a fault on hs2. od1 reports the absence or presence of a fault on hs1. lsb od0 reports the absence or presence of a fault on hs0. table 4. serial output bit assignment (continued) table 5. fail-safe operation and transitions to other 33888 modes wake rst wdto hs0 hs2 ls[4:11], hs[1,3] comments 0 0 x off off off device in sleep mode. 1 0 no off off off all outputs are off. when rst transitions to logic [1], device is in default. 1 0 yes on on off fail-safe mode. device reset into default mode by transitioning wake to logic [0]. 0 1 no s s s device in normal operating mode. 0 1 yes on on off fail-safe mode. device reset into default mode by transitioning rst to logic [0]. 1 1 no s s s device in normal operating mode. 1 1 yes on on off fail-safe mode. device reset into default mode by transitioning rst and wake to logic [0]. assumptions: normal operating vo ltage and junction temperatures, fsi terminal floating. x=don?t care. s=state determined by spi and/or direct input configurations. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
33888 motorola analog integrated circuit device data 24 default mode the default mode describes the st ate of the device after first applying v pwr voltage or a reset transition from logic [0] to logic [1] prior to spi communicat ion. in the default mode, all outputs will be off (assuming that the direct inputs ils and ihs[0:3] and the wake terminal ar e at logic [0]). all of the specific terminal functions wi ll operate as though all of the addressable configuration register bi ts were set to logic [0]. this means, for example, that all of the low-side outputs will be controllable by the ils terminal, and that all high-side outputs will be controllable via their respective ihs terminals. during the default mode, all high-side driv ers will default with open load detection enabled. all low-side drivers will default with open load detection disabled. this mode allows limited control of the 33888 with the direct inputs in the absence of a n spi. returning the device to the default state after a period of normal operation, followed by the removal of the v pwr voltage, requires that the rst input be held at a logic [0] state until v pwr falls to a level below 2.0 v. if the rst and v dd input levels are normal, then failure to allow v pwr to fall below 2.0 v will result in an internal bias circuit clamping the v pwr terminal to approximately 3.5 v. once v pwr falls below 2.0 v, the rst can be returned to 5.0 v without re-enabling the bias circuit. fault logic requirements the 33888 indicates all of the following faults as they occur: ? overtemperature fault ? overvoltage fault ? open load fault ? overcurrent fault with the exception of the overvo ltage, these faults are output specific. the overvoltage fault is a global fault. the overcurrent fault is only reported for the low-side outputs. the 33888 low-side outputs incorporate an internal fault filter, t dly( fs ) . the fault timer filters noise and switching transients for overcurrent faults when the output is on and open load faults when the output is off. all faults are latched and indicated by a logic [1] for each output in t he 33888 status word ( table 4 , page 23). if the fault is removed, the status bit for the faulted output will be cleared by a rising edge on cs . the fs terminal is driven to a logic [0] when a fault exists on any of the outputs. fs provides real time monitoring of the overvoltage fault. for the high-side outputs, fs provides real time monitoring of the open load and overtemperature. for the low-side outputs, the fs is latched to a logic [0] for open load, overtemperature, and overcurrent faults. the latch is cleared by toggling the state of the faulted output or by bringing rst low. overtemperature fault the 33888 incorporates over temperature detection and shutdown circuitry into each individual output structure. overtemperature detection occurs when an output is in the on state. when an output is shut down due to an overtemperature condition, no other out put is affected. the output experiencing the fault is shut down to protect it self from damage. a fault bit is loaded into the status register if the overtemper ature condition is removed, and the fault bit is cleared upon the rising edge of cs . for the low-side outputs, the faulted output is latched off during an overtemperature condition. if the temperature falls below the recovery level, t lim(hys) , then the output can be turned back on only after the output has first been commanded off either through the spi or the ils, depending on the logic configuration. for the high-side output(s), an overtemperature condition will result in the output(s) turning off until the temperature falls below the t lim(hys) . this cycle will conti nue indefinitely until action is taken by the mcu to shut the output(s) off. overvoltage fault the 33888 shuts down all out puts during an overvoltage condition on the v pwr terminal. the outputs remain in the off state until the overvoltage conditi on is removed. fault status for all outputs is latched into the status register. following an overvoltage conditi on, the next write cycle sent by the so terminal of the 33888 is logic [1] on od11:od0, indicating all outputs have shut down. if the overvoltage condition is removed, the status register can be cleared by a rising edge on cs . open load fault the 33888 incorporates open load detection circuitry on every output. a high-side or low- side output open load fault is detected and reported as a fault condition when the corresponding output is disabled (off) if it was configured for open load detection by setting the appropriate bit to logic [0] (hs3:hs0) or logic [1] (ls11:ls4) in the olfcr register ( figure 6 , page 25). the high-side open load fault is detected and latched into the status register after the internal gate voltage is pulled low enough to turn off the output. if the open load fault is removed or if the faulted output is comm anded on, the status register can be cleared by a rising edge on cs . note that the device default state will enable the high-side open load detection and disable the low-side open load det ection circuits, respectively. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola analog integrated circuit device data 33888 25 figure 6. low-side output off open load detection overcurrent fault requirements: low-side output an overcurrent condition is defined as any current value greater than i lim (500 ma minimum value for ls5, ls7, ls9, ls11, and 800 ma minimum value for ls4, ls6, ls8, ls10). the status of the correspondi ng bit in the cloccr register determines whether a specific output shuts down or continues to operate in an analog current limited mode until either the overcurrent condition is removed or the thermal shutdown limit is reached ( figure 7 , page 26). if the overcurrent shutdown mode is disabled, the fault reporting is disabled as well. for the low-side output of interest, if a d11:d4 bit was set to a logic [1] in the olcr register, the overcurrent protection shutdown circuitry will be enabled for that output. when a low- side output is commanded on either from the spi or the ils terminal, the drain of the low-side driver will be monitored for a voltage greater than the fault detection threshold (3.0 v typical). if the drain voltage exceeds this threshold, a timer will start and the output will be turned off and a fault latched in the status register after the timeout expire s. the faulted output can be retried only by commanding the output off and back on either through the spi or the ils terminal, depending on the logic configuration. if the fault is gone, the retried output will return to normal operation and the status register can be cleared on a rising edge of cs . if the fault remains, the retried output will latch off after the fault timer expires and the fault bit will remain set in the status register. for the low-side output of interest, if a d11:d4 bit was set to a logic [0] in the olcr register, the output experiencing an overcurrent condition is not di sabled until an overtemperature fault threshold has been reached. the specific output goes into an analog current limit mode of operation, i lim . the 33888 uses overtemperature shutdown to prot ect all outputs in this mode of operation. if the overcurrent co ndition is removed before the output has reached its overtemp erature limit, the output will function as if no fault has occurred. note that each pair of low-side drivers, ls4:ls5, ls6:ls7, ls8:ls9, and ls10:ls11, consists of a 500 ma and a 800 ma output. each pair of outputs shares ground bondwires. the bondwires are not rated to handle both outputs in current limit mode simultaneously. overcurrent fault requir ements: high-side output for the high-side output of in terest, the output current is limited to one of four levels depending on the type of high-side output, the amount of time that has elapsed since the output was switched on, and the st ate of the cloccr register. assuming that bits d3:d0 of the cloccr register are at logic [0], the current limit levels of the outputs will be initially at their peak levels as specified by the i lim(pk)hs[0:3] . after the high-side output is switched on, the peak current timer starts. after a period of time t pct , the current limit level changes to the sustain levels i limsushs[x,x] . for the high-side output of inte rest, if a d3:d0 bit of the cloccr is at logic [1], then the assigned output will only current limit at the sust ain level specified by i limsushs[x,x] . current is limited until the ov ertemperature circuitry shuts off the device. the device turns on automatically when the temperature fails below the t lim(hys) . this cycle continues indefinitely until action is tak en by the master to shut the output(s) off. reverse battery requirements the low-side and high-side outputs survive the application of reverse battery as low as -16 v. ground disconnect protection in the event that the 33888 ground is disconnected from load ground, the device protects itself and safely turns off the outputs, regardless of the state of the output at the time of disconnection. output v thres mosfet r l v pwr low = logic 0 50 ma v ofd(thres)ls 2.0 v?4.0 v ? + 33888 v pwr r l out f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
33888 motorola analog integrated circuit device data 26 figure 7. low-side short circuit detection and analog current limit undervoltage shutdown requirements all outputs turn off at some ba ttery voltage below 6.0 v; for the a version, the low side shutdown at a lower value, v pwruv . however, as long as the level st ays above 5.0 v, the internal logic states within the device are designed to be sustained. this ensures that when the battery level then rises above 6.0 v, the device will return to the state that it was in prior to the excursion between 5.0 v and 6.0 v (assuming that there was no spi communication or direct input changes during the event). if the battery voltage falls to a level below 5.0 v, then the internal logic is reinitialized and the devi ce is then in the default state upon the return of leve ls in excess of 6.0 v. output voltage clamping each output has an internal clamp to provide protection and dissipate the energy stored in inductive loads. each clamp independently limits the drain-to -source voltage to the range specified in the power outputs section of the static electrical characteristics table beginning on page 12. also see figure 8 . figure 8. low-side output voltage clamping v thres v ofd(thres)ls 2.0 v?4.0 v analog digital ? + ? + high = fault mosfet on v ref v pwr r l out 33888 v pwr time gnd current area (i a ) clamp energy (e j = i a x v cl x t) drain voltage d ra i n- s ource clamp voltage (v cl = 53 v) drain-source on voltage (v ds(on) ) drain current (i d = 0.5 a) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola analog integrated circuit device data 33888 27 package information soldering information the 33888 is packaged in a surface mount power package intended to be soldered directly onto the printed circuit board. the device was qualified in accordance with jedec standards jesd22-a113-b and j-std-020a. the recommended reflow conditions are as follows: ? convection: 225c +5.0c/-0c ? vapor phase reflow (vpr): 215c to 219c ? infrared (ir)/convection: 225c +5.0c/-0c the maximum peak temperature during the soldering process should not exceed 230c. the time at maximum temperature should range from 10 seconds to 40 seconds maximum. applications typical application figure 9 shows a typical application for the 33888. figure 9. 33888 typical application diagram rst v dd fs wdin 8 x relay or led v dd v pwr v pwr mcu 65 w loads +5.0 v +5.0 v 4 4 ihs0:ihs3 33888 gnd spi csns2-3 csns0-1 ils fsi 65 w 21 w 5.0 w 21 w 5.0 w 10 k ? 8 x 0.5 ? 40 m ? 40 m ? 10 m ? 10 m ? a/d a/d r c1 r c2 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
33888 motorola analog integrated circuit device data 28 package dimensions 30x a 12 12 b 1 14 16 23 25 28 29 36 2x c 0.1 pin number reference only pin 1 index area m m detail g 2.2 2.20 0.05 2.0 1.95 0.00 c 0.1 c 0.05 c seating plane 4 detail g view m-m (bottom view) (top view) a 0.1 b c 11.7 11.3 a 0.1 b c 8.70 8.30 2x 3.75 0.5 ( 2x 0.75) ( 2x 0.75) ( 2x 0.5) ( 2x 1.25) m 0.1 c m 0.05 c a b 2x 2.95 2.55 m 0.1 c m 0.05 c a b 2x 2.2 1.8 4x 0.2 0.0 6x 1.25 1.00 4x 2.0 1.5 4.45 4.05 1.45 1.05 a 0.1 b c a 0.1 b c 3.85 3.45 a 0.1 b c 0.40.2 2 places x 0.50.2 0.90 0.65 m 0.1 c m 0.05 c a b 30x 2x 0.62 0.48 10x 1.60 1.35 10x 1.20 0.95 5 a 0.1 b c 7.3 6.9 4.05 13x 0.8 0.4 6 6 1 0.6 2.875 7x 0.8 (0.25) (0.05) 1.625 3 2x 2.8 2.3 (0.3) 1 36 29 28 27 26 25 24 15 23 16 14 4x c 0.1 case 1438-06 issue e notes: 1. 2. 3. 4. 5. 6. all dimensions are in millimeters. dimensioning and tolerancing per asme y14.5m, 1994. the complete jedec designator for this package is: hf-pqfp-n. coplanarity applies to leads and corner leads. metal pads connected to the gnd. minimum metal gap should be 0.25mm. pnb suffix apnb suffix 36-terminal pqfn nonleaded package case 1438-06 issue e f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola analog integrated circuit device data 33888 29 c a4 a 64x seating plane h a2 b m aaa c a b e3 datum plane detail y 5 3 notes: 1. dimensions are in millimeters. 2. interpret dimensions and tolerances per asme y14.5m, 1994. 3. datum plane -h- is located at bottom of lead and is coincident with the lead where the lead exits the plastic body at the bottom of the parting line. 4. dimensions "d1" and "e1" do not include mold protrusion. allowable protrusion is 0.15 per side. dimension "d1" and "e1" do include mold mismatch and are determined at datum plane -h-. 5. dimension "b" does not include dambar protrusion. allowable dambar protrusion shall be 0.127 total in excess of the "b" dimension at maximum material condition. 6. datums -a- and -b- to be determined at datum plane -h-. dim min max millimeters a --- 3.15 a1 --- 0.25 a2 2.5 2.9 a3 0 0.1 a4 d d1 d2 12.5 12.9 d3 9.3 9.7 d4 13.4 13.6 e e1 e2 e3 l 0.8 1.1 b b1 0.22 0.33 c c1 e 0.65 bsc e1 h --- 0.8 aaa 0.12 0? bbb 0.2 ccc 0.1 0.8 1 16.95 17.45 13.9 14.1 13.9 14.1 2.35 2.65 9.3 9.7 16.95 17.45 0.22 0.38 0.23 0.32 0.23 0.29 2.925 bsc 7? e1 64 20 1 53 d 2x 52 33 21 32 e m bbb c a 58x e1 4x e m bbb c b e2 e/2 2x d1 d2 h h a 4 4 6 6 b pin one id d3 d4 e3 bottom view b1 b section w-w c c1 a1 (1.6) l 0.35 a3 detail y w w ccc gauge plane fb suffix 64-terminal pqfp plastic package case 1315-03 issue b f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
33888 motorola analog integrated circuit device data 30 notes f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
motorola analog integrated circuit device data 33888 31 notes f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
how to reach us: usa/europe/locations not listed: japan: motorola japan ltd.; sps, technical information center motorola literature distribution 3-20-1 minami-azabu. minato-ku, tokyo 106-8573, japan p.o. box 5405, denver, colorado 80217 81-3-3440-3569 1-800-521-6274 or 480-768-2130 asia/pacific: motorola semiconductors h. k. ltd.; silicon harbour centre 2 dai king street, tai po industrial estate, tai po, n.t., hong kong 852-26668334 home page: http://motorola.com/semiconductors mc33888 information in this document is provided solely to enable system and software implem enters to use motorola products. there are no express or implied copyright licenses granted hereunder to desig n or fabricate any integrated circuits or integrated circuits based on the informa tion in this document. motorola reserves the right to make changes without further noti ce to any products herein. motorola makes no warranty, represen tation or guarantee regarding the suitability of its products for any particular purpose, nor does motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters which may be provided in motorola data sheets and/or s pecifications can and do vary in different applications and actual performance may var y over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. motorola does not convey any license under its patent rights nor the rights of others. motorola pro ducts are not designed, intended, or authorized for use as compon ents in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in whic h the failure of the motorola product could create a situation where personal injury or death may occur. should buyer purchase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its officers, employees, subsidiaries, affiliates, and di stributors harmless against all claims, costs, damages, and expenses , and reasonable attorney fees arising out of, directly or indirectly, any claim of persona l injury or death associated with such unintended or unauthorized use, even if such claim a lleges that motorola was negligent regarding the design or manufa cture of the part. motorola and the stylized m logo are registered in the us patent and trademark office. all other product or service names are t he property of their respective owners. ? motorola, inc. 2004 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .

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